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TMP92CM22
2007-02-16
92CM22-152
(9) Transmission buffer
The transmission buffer (SC0BUF) shifts out and sends the transmission data
written from the CPU form the least significant bit in order. When all the bits are
shifted out, the transmission buffer becomes empty and generates an INTTX0
interrupt.
(10) Parity control circuit
When SC0CR<PE> in the serial channel control register is set to 1, it is possible to
transmit and receive data with parity. However, parity can be added only in 7-bit
UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel
control register allows either even or odd parity to be selected.
In the case of transmission, parity is automatically generated when data is written
to the transmission buffer SC0BUF. The data is transmitted after the parity bit has
been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit
UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission
data is written to the transmission buffer.
In the case of receiving, data is shifted into receiving buffer 1, and the parity is added
after the data has been transferred to receiving buffer 2 (SC0BUF), and then compared
with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit UART mode.
If they are not equal, a parity error is generated and the SC0CR<PERR> flag is set.
(11) Error flags
Three error flags are provided to increase the reliability of data reception.
1. Overrun error <OERR>
If all the bits of the next data item have been received in receiving buffer 1 while
valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is
generated.
The below is a recommended flow when the overrun-error is generated.
(INTRX interrupt routine)
1) Read receiving buffer
2) Read error flag
3) if <OERR> = “1”
then
4) Set to disable receiving (Program “0” to SC0MOD0<RXE>)
5) Wait to terminate current frame
6) Read receiving buffer
7) Read error flag
8) Set to enable receiving (Program “1” to SC0MOD0<RXE>)
9) Request to transmit again
10) Other