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TMP92CM22
2007-02-16
92CM22-178
3.10.5 Control in I
2
C Bus Mode
(1) Acknowledge mode specification
Set the SBI0CR1<ACK> to 1 for operation in the acknowledge mode. The
TMP92CM22 generates an additional clock pulse for an acknowledge signal when
operating in master mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In the
receiver mode during the clock pulse cycle, the SDA pin is set to the low in order to
generate the acknowledge signal.
Clear the <ACK> to 0 for operation in the non-acknowledge mode, the TMP92CM22
does not generate a clock pulse for the acknowledge signal when operating in the
master mode.
(2) Select number of transfer bits
The SBI0CR1<BC2:0> is used to select a number of bits for next transmission/
receiving data.
Since the <BC2:0> is cleared to 000 as a start condition, a slave address and
direction bit are transferred in 8 bits. Other than these, the <BC2:0> retains a
specified value.
(3) Serial clock
1. Clock source
The SBI0CR1<SCK2:0> is used to select a maximum transfer frequency outputted
on the SCL pin in master mode. Set the baud rates, which have been calculated
according to the formula below, to meet the specifications of the I
2
C bus, such as the
smallest pulse width of t
LOW
.
SBI0CR1<SCK2:0> n
000 5
001 6
010 7
011 8
100 9
101 10
110 11
Note: f
SBI
shows f
SYS
.
Figure 3.10.7 Clock Source
t
HIGH
t
LOW
1/fscl
t
LOW
= 2
n
−
1
/f
SBI
t
HIGH
= 2
n
−
1
/f
SBI
+ 8/f
SBI
fscl = 1/(t
LOW
+ t
HIGH
)
f
SBI
2
n
+ 8
=