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TMP92CM22
2007-02-16
92CM22-128
TMRB0 Mode Register
7 6 5 4 3 2 1 0
Bit symbol − − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0TB0MOD
(1182H)
Read/Write R/W W R/W
After reset 0 0 1 0 0 0 0 0
Function Always
write “0”.
Always
write “0”.
Software
capture
control
0: Software
capturer
1: Undefined
Capture timing
00: Disable
01: (Reserved)
10: (Reserved)
11: TA1OUT↑ TA1OUT↓
Up counter
control
0: Clear
disable
1: Clear
enable
TMRB0 source clock
00: (Reserved)
01: φT1
10: φT4
11: φT16
00 Reserved
01 φT1
10 φT4
11 φT16
0 Disable
1 Enable clearing on match with TB0RG1H/L
Capture control
00 Disable
01 (Reserved)
10 (Reserved)
11 Capture to TB0CP0H/L at rising edge of TA1OUT
Capture to TB0CP1H/L at falling edge of TA1OUT
0 Capture value of up counter to TB0CP0H/L
1 Undefined
Figure 3.8.4 Register for TMRB
Input clock
Clear up counter 0(UC0)
Capture/interrupt timing
Software capture
Read-modify
-write
instruction is
prohibited