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APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
A-102 EPSON S1C33210 PRODUCT PART
A.4 SRAM (55ns)
SRAM interface setup examples – 55ns
Operating Read cycle
Write cycle
Output disable
frequency Wait cycle Read cycle delay time
20MHz 1 2 2 1.5
25MHz 2 3 3 1.5
33MHz 2 3 3 1.5
SRAM interface timing – 55ns
SRAM interface 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Read cycle>
Read cycle time tRC 55 – 3 90 3 120 2 100
Address access time tACC – 55 3 90 3 120 2 100
#CE access time tACS – 55 3 90 3 120 2 100
#OE access time tOE – 30 2.5 75 2.5 100 1.5 75
Output disable delay time tOHZ 0 30 1.5 45 1.5 60 1.5 75
<Write cycle>
Write cycle time tWC 55 – 3 90 3 120 2 100
Address enable time tAW 50 – 2.5 75 2.5 100 1.5 75
Write pulse width tWP 45 – 260 280 150
Input data setup time tDW 30 – 260 280 150
Input data hold time tDH 0 – 0.5 15 0.5 20 0.5 25
SRAM: 55ns, CPU: 33/25MHz, read cycle
tRC
tACC
tACS
tOE
BCLK
A[23:0]
#CEx
#RD
D[15:0]
RD data
tOHZ
SRAM: 55ns, CPU: 33/25MHz, write cycle
tWC
tAW
tWP
tDW
BCLK
A[23:0]
#CEx
#WP
D[15:0] WR data
tDH