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V DMA BLOCK: IDMA (Intelligent DMA)
S1C33210 FUNCTION PART EPSON B-V-3-1
V-3 IDMA (Intelligent DMA)
Functional Outline of IDMA
The DMA Block contains an intelligent DMA (IDMA), a function that allows control information to be programmed
in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by an interrupt factor that
occurs in some internal peripheral circuit.
Although an additional overhead for loading and storing control information in RAM may be incurred, this
intelligent DMA supports such functions as successive transfers, block transfers, and linking to another IDMA.
IDMA is invoked by an interrupt factor that occurs in some internal peripheral circuit or a software trigger, thereby
performing a data transfer according to the control information in RAM. When the transfer is completed, IDMA can
generate an interrupt or invoke another IDMA according to link settings.
Programming Control Information
The intelligent DMA operates according to the control information prepared in RAM. The control information can be
stored in either internal RAM or external RAM should the necessary area be allocated.
The control information is 3 words (12 bytes) per channel in size, and must be located at contiguous addresses
beginning with the base address that is set in the software application as the starting address of channel 0.
Consequently, an area of 384 words (1,536 bytes) in RAM is required in order for all of 128 channels to be used.
The following explains how to set the base address and the contents of control information. Before using IDMA,
make each the settings described below.
Setting the base address
Set the starting address of control information (starting address of channel 0) in the IDMA base address
register.
16 low-order bits: DBASEL[15:0](D[15:0]) / IDMA base address low-order register (0x48200)
12 high-order bits: DBASEH[11:0](D[11:0]) / IDMA base address high-order register (0x48202)
When initially reset, the base address is set to 0x0C003A0.
Notes: • The address you set in the IDMA base address register must always be a word (32-bit) boundary
address.
• Be sure to disable DMA transfers (IDMAEN = "0") before setting the base address. Writing to
the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1").
When the register is read, the read data is indeterminate.
Control information
Write the control information for the IDMA channels used to RAM.
The addresses at which the control information of each channel is placed are determined by the base address
and a channel number.
Starting address of channel = base address + (channel number × 12 [bytes])
Note: The control information must be written only when the channel to be set does not start a DMA
transfer. If a DMA transfer starts when the control information is being written to the RAM, proper
transfer cannot performed. Reading the control information can always be done.