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III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
S1C33210 FUNCTION PART EPSON B-III-10-41
RXOVR: HDLC Rx overrun detected (D7) / HDLC Sp INT receive status register (0x020032E)
EOF: HDLC end of frame detected (D6) / HDLC Sp INT receive status register (0x020032E)
SHFD: HDLC short frame detected (D0) / HDLC Sp INT receive status register (0x020032E)
These bits give the status for Sp INT interrupt triggers. Note that Sp INT interrupt requests lock the receive queue and
that reading the receive data register updates this register.
A "1" in RXOVR indicates that incoming data has overwritten receive queue data and that the queue contents are no
longer valid. The transition from "0" to "1" always produces an Sp INT interrupt request.
The only way to clear this bit and the corresponding Sp INT interrupt request is with an error reset command. Note,
however, that this command does not clear the queue. That requires writing "1" to the reset receive queue bit in the
receive control register.
A "1" in EOF indicates detection of a closing flag pattern. This bit remains in effect until the next frame or the next
error reset command. Whether the transition from "0" to "1" produces an Sp INT interrupt request depends on the Rx
INT mode and Rx INT and Sp INT setting.
A "1" in SHFD indicates a short frame, one with fewer than 32 bits. The transition from "0" to "1" always produces
an Sp INT interrupt request.
Clear this bit and the corresponding Sp INT interrupt request with an error reset command.
Note:The EOF Sp INT interrupt timing and queue operation are linked in the following ways.
1. Rx INT and Sp INT on queue threshold with a threshold setting of 0 –There is an Sp INT interrupt
request when the last byte, the one immediately before the closing flag pattern, reaches the
receive data register, the head of the receive queue.
2. Rx INT and Sp INT on queue threshold with a nonzero threshold setting
There is an Sp INT interrupt request when the last byte enters the receive data register from the
receive shift register. Note that the software must read the EOF bit to determine whether the Sp
INT interrupt request is from some other source.
3. Rx INT and Sp INT on first receive character or Sp INT only
There is an Sp INT interrupt request when the software reads the last byte from the receive data
register. The hardware locks the queue and the data in the receive data register. Unlock the
queue with an error reset command.
ESINT: HDLC E/S INT monitored (D7) / HDLC monitor register (0x0200336)
SPINT: HDLC Sp INT monitored (D6) / HDLC monitor register (0x0200336)
RXINT: HDLC Rx INT monitored (D5) / HDLC monitor register (0x0200336)
TXINT: HDLC Tx INT monitored (D4) / HDLC monitor register (0x0200336)
These bits monitor the status of the corresponding HDLC interrupts.
ESINT monitors the status of the E/S INT interrupt.
SPINT monitors the status of the Sp INT interrupt.
RXINT monitors the status of the Rx INT interrupt.
TXINT monitors the status of the Tx INT interrupt.
Reading this register returns the interrupt status at the time of the read. Writes to these bits are ignored.