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APPENDIX: I/O MAP
B-APPENDIX-38 EPSON S1C33210 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D1ADRL15
D1ADRL14
D1ADRL13
D1ADRL12
D1ADRL11
D1ADRL10
D1ADRL9
D1ADRL8
D1ADRL7
D1ADRL6
D1ADRL5
D1ADRL4
D1ADRL3
D1ADRL2
D1ADRL1
D1ADRL0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 destination address[15:0]
S) Invalid
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048238
(HW)
High-speed
DMA Ch.1
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D1MOD1
D1MOD0
D1IN1
D1IN0
D1ADRH11
D1ADRH10
D1ADRH9
D1ADRH8
D1ADRH7
D1ADRH6
D1ADRH5
D1ADRH4
D1ADRH3
D1ADRH2
D1ADRH1
D1ADRH0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer mode
D) Ch.1 destination address
control
S) Invalid
D) Ch.1 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004823A
(HW)
High-speed
DMA Ch.1
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D1MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS1_EN
DF–1
D0
reserved
Ch.1 enable
1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004823C
(HW)
High-speed
DMA Ch.1
enable register
––
HS1_TF
DF–1
D0
reserved
Ch.1 trigger flag clear (writing)
Ch.1 trigger flag status (reading)
1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004823E
(HW)
High-speed
DMA Ch.1
trigger flag
register