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V DMA BLOCK: HSDMA (High-Speed DMA)
S1C33210 FUNCTION PART EPSON B-V-2-17
I/O Memory of HSDMA
Table 2.5 shows the control bits of HSDMA.
Table 2.5 Control Bits of HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PHSD1L2
PHSD1L1
PHSD1L0
–
PHSD0L2
PHSD0L1
PHSD0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.1
interrupt level
reserved
High-speed DMA Ch.0
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040263
(B)
High-speed
DMA Ch.0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD3L2
PHSD3L1
PHSD3L0
–
PHSD2L2
PHSD2L1
PHSD2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.3
interrupt level
reserved
High-speed DMA Ch.2
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040264
(B)
High-speed
DMA Ch.2/3
interrupt
priority register
–
EIDMA
EHDM3
EHDM2
EHDM1
EHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040271
(B)
1 Enabled 0 Disabled
DMA interrupt
enable register
–
FIDMA
FHDM3
FHDM2
FHDM1
FHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040281
(B)
DMA interrupt
factor flag
register
1 Factor is
generated
0 No factor is
generated
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040290
(B)
1 IDMA
request
0 Interrupt
request
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040294
(B)
1 IDMA
enabled
0 IDMA
disabled
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA enable
register