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APPENDIX: I/O MAP
B-APPENDIX-40 EPSON S1C33210 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D2ADRL15
D2ADRL14
D2ADRL13
D2ADRL12
D2ADRL11
D2ADRL10
D2ADRL9
D2ADRL8
D2ADRL7
D2ADRL6
D2ADRL5
D2ADRL4
D2ADRL3
D2ADRL2
D2ADRL1
D2ADRL0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 destination address[15:0]
S) Invalid
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048248
(HW)
High-speed
DMA Ch.2
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D2MOD1
D2MOD0
D2IN1
D2IN0
D2ADRH11
D2ADRH10
D2ADRH9
D2ADRH8
D2ADRH7
D2ADRH6
D2ADRH5
D2ADRH4
D2ADRH3
D2ADRH2
D2ADRH1
D2ADRH0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer mode
D) Ch.2 destination address
control
S) Invalid
D) Ch.2 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004824A
(HW)
High-speed
DMA Ch.2
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D2MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS2_EN
DF–1
D0
reserved
Ch.2 enable
1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004824C
(HW)
High-speed
DMA Ch.2
enable register
––
HS2_TF
DF–1
D0
reserved
Ch.2 trigger flag clear (writing)
Ch.2 trigger flag status (reading)
1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004824E
(HW)
High-speed
DMA Ch.2
trigger flag
register