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III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
S1C33210 FUNCTION PART EPSON B-III-10-37
RXADD[7:0]: HDLC receive address (D[7:0]) / HDLC receive address register (0x020030C)
This register specifies the address for filtering incoming frames based on the byte immediately following the
opening flag pattern.
If the HDLC receive operation settings register (D7/0x020030E) specifies address comparison, the hardware rejects
frames whose address fields do not match this value. Otherwise, it accepts them all.
If the HDLC receive operation settings register (D6/0x020030E) specifies half-byte comparison, the above
comparison uses only the top four bits of the address.
Note that frames with 0xFF (global address) in the address byte are unconditionally accepted; those with 0x00 (no
station address), always rejected.
ADDCE: HDLC address compare enable (D7) / HDLC receive operation settings register (0x0200030E)
ADDCM:HDLC address compare mode (D6) / HDLC receive operation settings register (0x0200030E)
IDLDE: HDLC idle detect enable (D5) / HDLC receive operation settings register (0x0200030E)
SHFDE: HDLC short frame detect enable (D4) / HDLC receive operation settings register (0x0200030E)
These bits control HDLC receive operation.
Setting ADDCE to "1" enables comparison of the byte immediately following the opening flag pattern with the
contents of the HDLC receive address register. Otherwise, the hardware accepts all frames.
Note that ADDCM specifies the number of bits for the comparison.
Write "1": Enable
Write "0": Disable
ADDCM specifies the number of bits for the address comparison, if enabled: "0" for full (8 bits) or "1" for half (top 4
bits). This setting is only valid when ADDCE is "1."
Setting IDLDE to "1" enables the detection of idle states.
Write "1": Enable the detection
Write "0": Disable the detection
Setting SHFDE to "1" enables the detection of short frames, ones with fewer than 32 bits.
Write "1": Enable the detection
Write "0": Disable the detection
Note that frame filtering has no effect on abort detection. An abort pattern produces the same results as when address
comparison is disabled.
RXFTH[2:0]: HDLC receive queue interrupt threshold (D[2:0]) / HDLC receive queue interrupt threshold
register (0x0200310)
These bits specify the queue level for triggering receive queue interrupts:
0 for the first byte entering the queue (receive character available),
3 for the fourth (half full),
7 for the eighth (full), etc.