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TABLE OF CONTENTS
iv EPSON
Bus Speed Mode...............................................................................................................................B-II-4-17
Bus Clock Output...............................................................................................................................B-II-4-17
Bus Cycles in External System Interface................................................................................................B-II-4-18
SRAM Read Cycles...........................................................................................................................B-II-4-18
Bus Timing............................................................................................................................................B-II-4-19
SRAM Write Cycles...........................................................................................................................B-II-4-20
Burst ROM Read Cycles.................................................................................................................B-II-4-22
DRAM Direct Interface....................................................................................................................................B-II-4-23
Outline of DRAM Interface.............................................................................................................B-II-4-23
DRAM Setting Conditions...............................................................................................................B-II-4-24
DRAM Read/Write Cycles...............................................................................................................B-II-4-27
DRAM Refresh Cycles.....................................................................................................................B-II-4-30
Releasing External Bus.................................................................................................................................B-II-4-31
Power-down Control by External Device................................................................................................B-II-4-32
I/O Memory of BCU.........................................................................................................................................B-II-4-33
II-5 ITC (Interrupt Controller) .................................................................................B-II-5-1
Outline of Interrupt Functions.........................................................................................................................B-II-5-1
Maskable Interrupts.............................................................................................................................B-II-5-1
Interrupt Factors and Intelligent DMA...........................................................................................B-II-5-3
Nonmaskable Interrupt (NMI)..........................................................................................................B-II-5-3
Interrupt Processing by the CPU....................................................................................................B-II-5-3
Clearing Standby Mode by Interrupts...........................................................................................B-II-5-3
Trap Table.............................................................................................................................................................B-II-5-4
Control of Maskable Interrupts......................................................................................................................B-II-5-5
Structure of the Interrupt Controller...............................................................................................B-II-5-5
Processor Status Register (PSR)...................................................................................................B-II-5-5
Interrupt Factor Flag and Interrupt Enable Register...............................................................B-II-5-6
Interrupt Priority Register and Interrupt Levels.........................................................................B-II-5-8
IDMA Invocation..................................................................................................................................................B-II-5-9
HSDMA Invocation...........................................................................................................................................B-II-5-11
I/O Memory of Interrupt Controller.............................................................................................................B-II-5-12
Programming Notes.........................................................................................................................................B-II-5-25
II-6 CLG (Clock Generator) ....................................................................................B-II-6-1
Configuration of Clock Generator.................................................................................................................B-II-6-1
I/O Pins of Clock Generator...........................................................................................................................B-II-6-2
High-Speed (OSC3) Oscillation Circuit.......................................................................................................B-II-6-2
PLL .........................................................................................................................................................................B-II-6-3
Controlling Oscillation.......................................................................................................................................B-II-6-3
Setting and Switching Over the CPU Operating Clock.........................................................................B-II-6-4
Power-Control Register Protection Flag....................................................................................................B-II-6-5
Operation in Standby Mode...........................................................................................................................B-II-6-5
I/O Memory of Clock Generator....................................................................................................................B-II-6-6
Programming Notes...........................................................................................................................................B-II-6-9
II-7 DBG (Debug Unit)............................................................................................B-II-7-1
Debug Circuit........................................................................................................................................................B-II-7-1
I/O Pins of Debug Circuit.................................................................................................................................B-II-7-1