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III PERIPHERAL BLOCK: CLOCK TIMER
S1C33210 FUNCTION PART EPSON B-III-7-5
An interrupt can be generated on a specified alarm day at a specified time as described in the preceding section.
Interrupts generated by a signal and those generated by an alarm can both be used. However, since the clock
timer has only one interrupt factor flag, it is the same interrupt that is generated by the timer. Therefore, if both
types of interrupts are used, when an interrupt occurs, read the interrupt factor generation flag TCIF and alarm
factor generation flag TCAF to determine which factor has generated the interrupt.
Once the factor generation flag is set to "1", it remains set until it is reset by writing "1" in the software. After
confirming that the flag is set, write "1" to reset it.
The interrupt factor generation flag TCIF and alarm factor generation flag TCAF should be reset after at least 4
ms have passed from generation of an interrupt or an alarm.
Note: To prevent generation of an unwanted interrupt, disable the clock timer interrupt before selecting
the interrupt and alarm factors. Then, before reenabling the interrupt, reset each factor generation
flag and the interrupt factor flag.
Control registers of the interrupt controller
The following lists the clock timer interrupt control registers:
Interrupt factor flag: FCTM (D1) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
Interrupt enable: ECTM (D1) / Port input 4–7, clock timer, A/D interrupt enable register (0x40277)
Interrupt level: PCTM[2:0] (D[2:0]) / Clock timer interrupt priority register (0x4026B)
When an interrupt factor occurs, the clock timer sets the interrupt actor flag to "1" as described above. At this
time, if the interrupt enable register bit is set to "1", an interrupt request is generated.
Interrupts can be disabled by leaving the interrupt enable register bit reset to "0". The interrupt factor flag is
always set to "1" when an interrupt factor is generated, regardless of the setting of the interrupt enable register
(even when it is set to "0").
The interrupt priority register sets the priority levels (0 to 7) of interrupts. An interrupt request to the CPU is
accepted on the condition that no other interrupt request has been generated that is of a higher priority.
It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the clock
timer interrupt level set by the interrupt priority register that a clock timer interrupt request is actually accepted
by the CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
Note that the clock timer interrupt factor does not have a function to invoke an intelligent DMA.
Trap vectors
The trap vector addresses for the clock-timer interrupt by default are set to 0x0C00104.
The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).