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APPENDIX: I/O MAP
B-APPENDIX-36 EPSON S1C33210 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D0ADRL15
D0ADRL14
D0ADRL13
D0ADRL12
D0ADRL11
D0ADRL10
D0ADRL9
D0ADRL8
D0ADRL7
D0ADRL6
D0ADRL5
D0ADRL4
D0ADRL3
D0ADRL2
D0ADRL1
D0ADRL0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 destination address[15:0]
S) Invalid
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048228
(HW)
High-speed
DMA Ch.0
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D0MOD1
D0MOD0
D0IN1
D0IN0
D0ADRH11
D0ADRH10
D0ADRH9
D0ADRH8
D0ADRH7
D0ADRH6
D0ADRH5
D0ADRH4
D0ADRH3
D0ADRH2
D0ADRH1
D0ADRH0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer mode
D) Ch.0 destination address
control
S) Invalid
D) Ch.0 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004822A
(HW)
High-speed
DMA Ch.0
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D0MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS0_EN
DF–1
D0
reserved
Ch.0 enable
1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004822C
(HW)
High-speed
DMA Ch.0
enable register
––
HS0_TF
DF–1
D0
reserved
Ch.0 trigger flag clear (writing)
Ch.0 trigger flag status (reading)
1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004822E
(HW)
High-speed
DMA Ch.0
trigger flag
register