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APPENDIX: I/O MAP
S1C33210 FUNCTION PART EPSON B-APPENDIX-27
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
A18AS
A16AS
A14AS
A12AS
–
A8AS
A6AS
A5AS
A18RD
A16RD
A14RD
A12RD
–
A8RD
A6RD
A5RD
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 address strobe signal
Area 16, 15 address strobe signal
Area 14, 13 address strobe signal
Area 12, 11 address strobe signal
reserved
Area 8, 7 address strobe signal
Area 6 address strobe signal
Area 5, 4 address strobe signal
Area 18, 17 read signal
Area 16, 15 read signal
Area 14, 13 read signal
Area 12, 11 read signal
reserved
Area 8, 7 read signal
Area 6 read signal
Area 5, 4 read signal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0 when being read.
0048138
(HW)
G/A read signal
control register
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
–
A1X1MD
–
BCLKSEL1
BCLKSEL0
D7–4
D3
D2
D1
D0
reserved
Area 1 access-speed
reserved
BCLK output clock selection
1
1
0
0
1
0
1
0
BCLKSEL[1:0]
–
–
BCLK
PLL_CLK
OSC3_CLK
BCU_CLK
CPU_CLK
0
0
0
0
0
–
R/W
–
R/W
0 when being read.
x2 speed mode only
0 when being read.
004813A
(B)
BCLK select
register
1 2 cycles 0 4 cycles