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III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
B-III-10-4 EPSON S1C33210 FUNCTION PART
List of Pin Functions
Table 10.2 lists the five mobile access interface pin configurations specified by the MSEL pin input level and
communications macro select (MCRS) register (D[1:0]/0x200000).
Table 10.2 Mobile Access Interface Pin Configurations
Pin Name I/O MSEL = Low MSEL = High Communications Mode
Serial IF Ch. 3
MCRS = (0, 0)
UART
communications
MCRS = (0, 0)
HDLC
communications
MCRS = (0, 1)
PDC
communications
MCRS = (1, 0)
PHS
communications
MCRS = (1, 1)
DTR
RTS
TXD
RI
CTS
DCD
DSR
RXD
O
O
O
I
I
I
I
I
DTR
RTS
SOUT3
RI
CTS
DCD
DSR
SIN3
DTR
RTS
SOUT
RI
CTS
DCD
DSR
SIN
MOPORT2
MOPORT3
TXD
MIPORT0
HDLCLK
–
MIPORT1
RXD
MOPORT2
MOPORT3
PDCUPD
MIPORT0
PDCCLK
PDCFRM
MIPORT1
PDCDWD
MOPORT2
MOPORT3
PHSUPD
MIPORT0
PHSCLK
PHSFRM
MIPORT1
PHSDWD
CNT1
CNT2
O
O
CNT1
CNT2
CNT1
CNT2
CNT1
CNT2
CNT1
CNT2
CNT1
CNT2
GOUT O GOUT GOUT GOUT GOUT GOUT
Note:Serial IF Ch. 3 requires both MSEL = Low and MCRS = (0, 0).
Basic Settings for Mobile Access Interfaces
Using the mobile access interfaces for communications requires the following basic settings.
Operating Clock
First use the CKD[3:0] bits in the communications block clock frequency divider register (D[3:0]/0x0200004)
to specify the ratio for internally converting the PERICLK clock signal from the CPU core to a lower frequency
(SCK) to conserve power. (See Table 10.3.) Specify the PERICLK frequency and then switch these bits to
produce a frequency between 5 MHz and 10 MHz.
The default setting, after an initial reset, is 1111, which specifies the highest divider (16) for the slowest clock.
Table 10.3 Clock Frequency Divider Settings
CKD3 CKD2 CKD1 CKD0 SCK Clock Frequency Divider
Settings
1111 fout/16
1110 fout/15
1101 fout/14
1100 fout/13
1011 fout/12
1010 fout/11
1001 fout/10
1000 fout/9
0111 fout/8
0110 fout/7
0101 fout/6
0100 fout/5
0011 fout/4
0010 fout/3
0001 fout/2
0000 fout/2
fout = PERICLK output frequency