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II CORE BLOCK: CPU AND OPERATING MODE
B-II-2-2 EPSON S1C33210 FUNCTION PART
Standby Mode
The CPU supports three standby modes: two HALT modes and a SLEEP mode.
By setting the CPU in the standby mode, power consumption can greatly be reduced.
HALT Mode
When the CPU executes the halt instruction, it suspends the program execution and enters the HALT mode.
The CPU supports two types of HALT modes (basic HALT mode and HALT2 mode) and either can be selected using
the HLT2OP (D3) / Clock option register (0x40190).
Since the CPU stops in basic HALT mode, current consumption is reduced proportionally. The internal peripheral
circuits retain their states (stopped or not stopped) at the point the halt instruction is executed.
HALT2 mode stops the external bus control functions including DMA and the bus clock as well as the CPU similar to
basic HALT mode. Consequently, HALT2 mode realizes more power saving than the basic HALT mode.
The HALT mode is canceled by an initial reset or an interrupt including NMI. This mode is useful for saving power
when waiting for an external input or completion of the peripheral circuit operations that do not need to execute the
CPU.
The CPU transits to program execution status through trap processing when the HALT mode is canceled by an
interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the
instruction that follows the executed halt instruction into the stack. Therefore, when the interrupt processing routine
is terminated by the reti instruction, the program flow returns to the instruction that follows the halt instruction.
Note that the HALT mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into
interrupt disabled status.
SLEEP Mode
When the CPU executes the slp instruction, it suspends the program execution and enters SLEEP mode.
In SLEEP mode, the CPU and the internal peripheral circuits including the high-speed (OSC3) oscillation circuit stop
operating. Thus SLEEP mode can greatly reduce current consumption in comparison to HALT mode. Moreover, the
low-speed (OSC1) oscillation circuit and clock timer do not stop operating. The clock function keeps operating in
SLEEP mode.
SLEEP mode is canceled by an initial reset or an interrupt (NMI, clock timer interrupt, external interrupt such as a
key entry). Note that other interrupts by the internal peripheral circuits that use the OSC3 clock cannot be used for
canceling SLEEP mode.
The CPU transits to program execution status through trap processing when the SLEEP mode is canceled by an
interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the
instruction that follows the executed slp instruction into the stack. Therefore, when the interrupt processing routine is
terminated by the reti instruction, the program flow returns to the instruction that follows the slp instruction.
Note that SLEEP mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into
interrupt disabled status.