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II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-12 EPSON S1C33210 FUNCTION PART
I/O Memory of Interrupt Controller
Table 5.3 shows the control bits of the interrupt controller.
Table 5.3 Control Bits of Interrupt Controller
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PP1L2
PP1L1
PP1L0
–
PP0L2
PP0L1
PP0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 1 interrupt level
reserved
Port input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040260
(B)
Port input 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP3L2
PP3L1
PP3L0
–
PP2L2
PP2L1
PP2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 3 interrupt level
reserved
Port input 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040261
(B)
Port input 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
PK1L2
PK1L1
PK1L0
–
PK0L2
PK0L1
PK0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Key input 1 interrupt level
reserved
Key input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040262
(B)
Key input
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD1L2
PHSD1L1
PHSD1L0
–
PHSD0L2
PHSD0L1
PHSD0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.1
interrupt level
reserved
High-speed DMA Ch.0
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040263
(B)
High-speed
DMA Ch.0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD3L2
PHSD3L1
PHSD3L0
–
PHSD2L2
PHSD2L1
PHSD2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.3
interrupt level
reserved
High-speed DMA Ch.2
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040264
(B)
High-speed
DMA Ch.2/3
interrupt
priority register
–
0 to 7
–
PDM2
PDM1
PDM0
D7–3
D2
D1
D0
reserved
IDMA interrupt level
–
X
X
X
–
R/W
0 when being read.0040265
(B)
IDMA interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T12
P16T11
P16T10
–
P16T02
P16T01
P16T00
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 interrupt level
reserved
16-bit timer 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040266
(B)
16-bit timer 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T32
P16T31
P16T30
–
P16T22
P16T21
P16T20
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 interrupt level
reserved
16-bit timer 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040267
(B)
16-bit timer 2/3
interrupt
priority register