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III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33210 FUNCTION PART EPSON B-III-4-5
• External clock
When using the timer as an event counter by supplying clock pulses from an external source, make sure the
event cycle is at least the CPU operating clock period.
Selecting comparison data register/buffer
The comparison data registers A and B are used to store the data to be compared with the content of the up-
counter. This register can be directly read and written. Furthermore, comparison data can be set via the
comparison register buffer. In this case, the set value is loaded to the comparison data register when the
counter is reset by the comparison match B signal or software (by writing "1" to PRESETx bit).
Select whether comparison data is written to the comparison data register or the buffer using the following
control bits:
Timer 0 comparison register buffer enable: SELCRB0 (D5) / 16-bit timer 0 control register (0x48186)
Timer 1 comparison register buffer enable: SELCRB1 (D5) / 16-bit timer 1 control register (0x4818E)
Timer 2 comparison register buffer enable: SELCRB2 (D5) / 16-bit timer 2 control register (0x48196)
Timer 3 comparison register buffer enable: SELCRB3 (D5) / 16-bit timer 3 control register (0x4819E)
Timer 4 comparison register buffer enable: SELCRB4 (D5) / 16-bit timer 4 control register (0x481A6)
Timer 5 comparison register buffer enable: SELCRB5 (D5) / 16-bit timer 5 control register (0x481AE)
When "1" is written to SELCRBx, the comparison register buffer is selected and when "0" is written, the
comparison data register is selected.
At initial reset, the comparison data register is selected.
Setting comparison data
The programmable timer contains two data comparators that allows the count data to be compared with given
values. The following registers are used to set these values.
Timer 0 comparison data A: CR0A[15:0] (D[F:0]) / 16-bit timer 0 comparison data A set-up register (0x48180)
Timer 0 comparison data B: CR0B[15:0] (D[F:0]) / 16-bit timer 0 comparison data B set-up register (0x48182)
Timer 1 comparison data A: CR1A[15:0] (D[F:0]) / 16-bit timer 1 comparison data A set-up register (0x48188)
Timer 1 comparison data B: CR1B[15:0] (D[F:0]) / 16-bit timer 1 comparison data B set-up register (0x4818A)
Timer 2 comparison data A: CR2A[15:0] (D[F:0]) / 16-bit timer 2 comparison data A set-up register (0x48190)
Timer 2 comparison data B: CR2B[15:0] (D[F:0]) / 16-bit timer 2 comparison data B set-up register (0x48192)
Timer 3 comparison data A: CR3A[15:0] (D[F:0]) / 16-bit timer 3 comparison data A set-up register (0x48198)
Timer 3 comparison data B: CR3B[15:0] (D[F:0]) / 16-bit timer 3 comparison data B set-up register (0x4819A)
Timer 4 comparison data A: CR4A[15:0] (D[F:0]) / 16-bit timer 4 comparison data A set-up register (0x481A0)
Timer 4 comparison data B: CR4B[15:0] (D[F:0]) / 16-bit timer 4 comparison data B set-up register (0x481A2)
Timer 5 comparison data A: CR5A[15:0] (D[F:0]) / 16-bit timer 5 comparison data A set-up register (0x481A8)
Timer 5 comparison data B: CR5B[15:0] (D[F:0]) / 16-bit timer 5 comparison data B set-up register (0x481AA)
When SELCRBx is set to "0", these registers allow direct reading/writing from/to the comparison data register.
When SELCRBx is set to "1", these registers are used to read/write from/to the comparison register buffer. The
content of the buffer is loaded to the comparison data register when the counter is reset.
At initial reset, the comparison data registers/buffers are not initialized.
The programmable timer compares the comparison data register and count data and, when the two values are
equal, generates a comparison match signal. This comparison match signal controls the clock output (TMx
signal) to external devices, in addition to generating an interrupt.
The comparison data B is also used to reset the counter.