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II CORE BLOCK: ITC (Interrupt Controller)
S1C33210 FUNCTION PART EPSON B-II-5-25
TTBR09–TTBR00: Trap table base address [9:0] (D[9:0]) / TTBR low-order register (0x48134[HW])
TTBR15–TTBR10: Trap table base address [15:10] (D[F:A]) / TTBR low-order register (0x48134[HW])
TTBR2B–TTBR20:Trap table base address [27:16] (D[B:0]) / TTBR high-order register (0x48136[HW])
TTBR33–TTBR30: Trap table base address [31:28] (D[F:C]) / TTBR high-order register (0x48136[HW])
Set the starting address of the trap table.
TTBR0 and TTBR3 are read-only registers and are fixed to "0". For this reason, the trap table starting address always
begins with a 1KB boundary address.
The TTBR registers normally are write-protected to prevent them from being inadvertently rewritten. To remove
this write protect function, another register, TBRP (D[F:8]) / TTBR write-protect register (0x4812D), is provided. A
write to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write to the most
significant byte of the TTBR register (0x48137). Consequently, writes to the TTBR register need to begin with the
low-order half-word first. However, since occurrences of NMI and the like between writes of the low-order and
high-order half-words cause malfunctions, it is recommended that the register be written in words.
After an initial reset, the TTBR register is set to 0x0C00000.
Programming Notes
(1) In cases when an interrupt factor that is used for restarting from the standby mode has been set to invoke IDMA,
IDMA is started up by the interrupt at its occurrence. In SLEEP mode, the high-speed (OSC3) oscillation
circuit also starts operating. However, if an interrupt to be generated upon completion of IDMA is disabled at
the setting of IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the
next interrupt request is generated.
(2) As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However,
since the interrupt priority register in the C33 Core Block consists of three bits, interrupt levels in each interrupt
system can only be set for up to 8.
(3) When the reset-only method is used to reset the interrupt factor flag (by writing "1"), if a read-modify-write
instruction (e.g., bset, bclr, or bnot) is executed, the other interrupt factor flags at the same address that have
been set to "1" are reset by a write. This requires caution. In cases when the read/write method is used to reset
the interrupt factor flag (by writing "0"), all factor flags for which "0" has been written are reset. When a
read-modify-write operation is performed, an interrupt factor may occur between reads and writes, so be
careful when using this method.
The same applies to the set-only method and read/write method for the IDMA request and IDMA enable
registers.
(4) After an initial reset, the interrupt factor flags and interrupt priority registers all become indeterminate. To
prevent unwanted interrupts or IDMA requests from being generated inadvertently, be sure to reset these flags
and registers in the software application.
(5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt, be
sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti
instruction.