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V DMA BLOCK: HSDMA (High-Speed DMA)
S1C33210 FUNCTION PART EPSON B-V-2-35
RHDM0: Ch.0 IDMA request (D4) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA request register (0x40290)
RHDM1: Ch.1 IDMA request (D5) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA request register (0x40290)
Specify whether IDMA need to be invoked when an interrupt factor occurs.
When using the set-only method (default)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read/write method
Write "1": IDMA request
Write "0": Interrupt request
Read: Valid
RHDM0 and RHDM1 are the IDMA request bits for HSDMA channels 0 and 1, respectively. If the bit is set to "1",
IDMA is invoked when an interrupt factor occurs, thus performing a programmed data transfer. If the register is set
to "0", regular interrupt processing is performed without ever invoking IDMA.
For details on IDMA, refer to "IDMA (Intelligent DMA)".
At initial reset, RHDMx is set to "0" (interrupt request).
DEHDM0:
Ch.0 IDMA enable (D4) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294)
DEHDM1: Ch.1 IDMA enable (D5) / Port input 0–3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294)
Enables IDMA transfer by means of an interrupt factor.
When using the set-only method (default)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read/write method
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
DEHDM0 and DEHDM1 are the IDMA enable bits for HSDMA channels 0 and 1, respectively. If DEHDMx is set to
"1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled.
At initial reset, DEHDMx is set to "0" (IDMA disabled).