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II CORE BLOCK: CLG (Clock Generator)
S1C33210 FUNCTION PART EPSON B-II-6-9
Programming Notes
(1) Immediately after the high-speed (OSC3) oscillation circuit is turned on, a certain period of time is required for
oscillation to stabilize (for a 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from
operating erratically, do not use the clock until its oscillation has stabilized.
In particular, if the CPU is set in SLEEP mode during operation using the OSC3 clock, the high-speed (OSC3)
oscillation circuit is turned off during in SLEEP mode and starts oscillating again after SLEEP mode is exited.
To prevent the CPU from operating erratically at restart due to an unstable OSC3 clock, set a sufficient
stabilization waiting time in 8-bit programmable timer 1 to turn on the oscillation stabilization waiting function
after SLEEP mode is exited before entering SLEEP mode.
(2) The oscillation circuit used for the CPU operating clock cannot be turned off.
(3) The CPU operating clock can only be switched over when both the OSC3 and OSC1 oscillation circuits are on.
Furthermore, when turning off an oscillation circuit that has become unnecessary as a result of the CPU
operating clock switchover, be sure to use separate instructions for switchover and oscillation turnoff. If these
two operations are processed simultaneously using one instruction, the CPU may operate erratically.
(4) If the high-speed (OSC3) oscillation circuit is turned off, all peripheral circuits operated using the OSC3 clock
will be inactive.
(5) If the OSC3 clock is unnecessary, use the OSC1 clock to operate the CPU and turn the high-speed (OSC3)
oscillation circuit off. This helps reduce current consumption.
(6) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode,
not HALT2 mode, with a setting of 0 in clock option register HLT20 (0x0040190 bit 3), that operation will be
an unpredictable erroneous operation.
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution,
erroneous operation will result. Ensure that DMA is not invoked in HALT mode.
In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped.
(7) In the SLEEP state, the oscillator circuit clock stops. In HALT2 mode, clock supply to the peripheral circuits
continues in the state (clock stopped/operating) immediately prior to the transition to the HALT2 state.
When restarting from this state, interrupt input from a port can be used as a trigger, but functionally, this
interrupt input operates as level input. Therefore, a level input based restart is performed even in the case of set
edge input.
Restart operation is as follows for rising and falling edges.
In case of rising edge interrupt setting: Restarted by high level input.
In case of falling edge interrupt setting:Restarted by low level input.
In normal operation, a restart begins following the elapse of a given time after execution of the SLP instruction,
but when restart by a falling (rising) level (edge) is set, the operation is as follows.
• The restart is effected immediately after execution of the SLP instruction.
• As ports are already at the low level when the SLP instruction is executed, there is no falling (rising) edge,
and therefore the SLP state is entered only momentarily, and the restart is effected immediately afterwards.
This is because there a synchronization circuit that uses the clock signal is inserted in the port input circuit. Also,
since the clock stops in the SLEEP state, and can stop in the HALT2 state, the circuit has a structure that
bypasses this synchronization circuit to restart. Therefore a restart occurs when the input level from the port is at
the active level.
Consequently, the system design should assume that a restart by means of port input from the SLEEP state or
HALT2 state is performed by level.