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89
iii) Return from a debug exception handler
n When a user program exception occurs at the same time as a Debug exception, change the DEPC
value so that a return will be made to the exception handler.
When NIS = 1, change DEPC to 0xBFC0 0000.
When OES = 1, change DEPC to 0x8000 0080 (if BEV = 0) or 0xBFC0 0180 (if BEV = 0).
n Executing a DERET instruction
PC: Contains the DEPC value.
Debug register DM: Cleared to 0.
Status register KUc, IEc: Set to 1, enabling interrupts.
The forced disabling of the cache auto-lock function is cleared and becomes governed by the
Cache register value.
Forced prohibition of Single Step exception is cleared, causing these to be governed by the
Debug register SSt.
NmI and debug exception masks are cleared.
(3) Exception priorities
DSS has a higher priority than DBp, since it occurs in the pipeline E stage. For this reason DSS is
not raised at the same time as DBp.
It is further possible for debug exceptions and user exceptions to occur simultaneously. In this case
processing branches first to the debug exception handler, but the Status, Cause, EPC and BadVAddr
registers are updated to the values for the user exception. DEPC is not automatically updated to the
user exception vector address, so the return address must be set by user software.
It is possible for DSS to occur at the same time as an instruction fetch Address Error AdEL or
instruction fetch TLB Refill exception (TLBL). DSS cannot occur simultaneously with any other
exceptions except these two.
The instruction that triggers the instruction fetch Address Error AdEL or instruction fetch TLB Refill
exception (TLBL) will not itself be executed, so it is not possible for DBp to occur at the same time as
these two exceptions.