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TMPR3901F
221
4.2.2 Burst Read
Burst read operation is used to refill a multiword area in cache memory. Because the second and each
succeeding data in a burst read operation can each be read in a single cycle, multiword data can be
read in from memory very quickly in this mode.
Burst read operation is issued whenever a cache miss occurs with either the instruction cache or data
cache. When Config register DCBR is cleared to 0 (setting the data cache refill size to one word), data
cache refill is accomplished with a single read operation. The burst refill size for each burst read
operation is set in the Config register IRSize field or DRSize field. The BSTSZ[1:0] signal outputs this
value.
Figure 4-3 shows the timing for a burst read cycle. At the start of a burst read, the BSTART* signal
is asserted for one clock only. At the same time, the RD* and BURST* signals are asserted. Then
the address A[31:2] and BE[3:0]* signals are latched, and the burst length setting in the Config
register is output at BSTSZ[1:0].
The TMPR3901F confirms that ACK* has been asserted and latches the data in the next clock cycle.
Addresses are incremented by +4 at each clock in which one data read takes place. In the case of a
burst read, the ACK* signal for the next data can be sampled in the same clock cycle as a data read.
In the clock cycle in which it is confirmed that the ACK* signal is active for the second from last data,
LAST* is asserted indicating that the next data transfer is the last one. LAST* is de-asserted in the
clock cycle in which it is confirmed that the ACK* signal is active for the last data.
RD* and BURST* are de-asserted in the clock in which the last data is read. BE[3:0]* and address
A[31:2] remain valid until the clock cycle in which the last data is read. The burst read cycle ends
with the clock cycle in which the last data is read.