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49
Table 6-2 shows the vector address of each exception and the values in the exception code (ExcCode) field of
the Cause register.
Table 6-2. Exception vector addresses and exception codes
Exception Mnemonic Vector address
†
Exception code
Reset Reset 0xBFC0 0000 (0xBFC0 0000) undefined
Non-maskable
Interrupt
NmI undefined
UTLB Refill UTLB(load) 0x8000 0000 (0xBFC0 0100) TLBL(2)
UTLB(store) TLBS (3)
TLB Refill TLBL (load) 0x8000 0080 (0xBFC0 0180) TLBL (2)
TLBS (store) TLBS (3)
TLB Modified Mod Mod (1)
Bus Error IBE (instruction) IBE (6)
DBE (data) DBE (7)
Address Error AdEL (load) AdEL (4)
AdES (store) AdES (5)
Overflow Ov Ov (12)
System Call Sys Sys (8)
Breakpoint Bp Bp (9)
Reserved
Instruction
RI Rl (10)
Coprocessor
Unusable
CpU CpU (11)
Interrupt Int Int (0)
Debug 0xBFC0 0200(0xBFC0 0200)
−
††
†
The addresses shown here are virtual addresses. The address in parentheses
applies when the Status register BEV bit is set to 1.
††
Cause of exception is shown in Debug register. See Chapter 8 for detail.