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Architecture
133
CACHE Cache CACHE
31 26 25 21 20 16 15 0
CACHE
101111
base op offset
6 5 5 16
Format :
CACHE op, offset(base)
Description :
Generates a virtual address by sign-extending the 16-bit offset and adding the result to the contents
of register base. The virtual address is translated to a physical address, and a 5-bit sub-opcode
designates the cache operation to be performed at that address.
If CP0 is unusable (in user mode), the Status register CP0 enable bit is cleared and a Coprocessor
Unusable exception is raised. The behavior of this instruction for operation and cache
combinations other than those listed in the table below, and when used with an uncached address, is
undefined.
Cache index operations (shown for bits 20 through 18 below) designate a cache block using part of
the virtual address.
For a directly mapped cache of 2
CACHESIZE
bytes with 2
BLOCKSIZE
bytes per tag, a block is designated
as vAddr
CACHESIZE-1
..
BLOCKSIZE
. In the case of a 2
WAYSIZE
-way set-associative cache of 2
CACHESIZE
bytes with 2
BLOCKSIZE
bytes per tag, a set is designated as vAddr
CACHESIZE-
WAYSIZE-1
..
BLOCKSIZE
.
A Cache hit operation (shown for bits 20 through 18 below) accesses the designated cache as an
ordinary data reference. If a cache block contains valid data for the generated physical address, it is a
hit and the designated operation is performed. In case of a miss, that is, if the cache block is invalid
or contains a different address, no operation is performed.
Bits 17..16 of the Cache instruction select the target cache as follows.
Bit#
Cache Cache
17 16
ID Name
0 0 I Instruction
0 1 D Data
1 0 - (reserved)
1 1 - (reserved)