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TMPR3901F
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5.3 Doze Mode
In this mode, the TMPR3901F stops internal operations the same as in Halt mode to reduce power dissipation.
However, in Doze mode bus arbitration and data cache snooping can continue. Setting the Config register
Doze bit to 1 switches from Active mode to Doze mode. During Doze mode, the TMPR3901F will assert the
DOZE signal and stall the pipeline in “holding current”status.
If an instruction attempts to switch to Doze mode (by setting the Config register Doze bit to 1) during a bus
operation, the DOZE signal will not be asserted until completion of the bus operation. If a switch to Doze
mode is attempted when a device other than the TMPR3901F owns the bus, the DOZE signal will not be
asserted until the TMPR3901F regains bus mastership. Write operations will continue even in Doze made, if
the write buffer contains data, until the buffer is emptied. SYSCLK and FCLK continue to run in Doze mode.
The TMPR3901F will recognize the BUSREQ* signal the same as in Active mode and will assert the
BUSGNT* signal to release bus mastership. Data cache snooping can continue even if the TMPR3901F does
not own the bus. When the other device gives up the bus and de-asserts the BUSREQ* signal, the TMPR3901F
will then de-assert the BUSGNT* signal and regain mastership of the bus.
The TMPR3901F can be returned from Doze mode to Active mode, and the Doze bit cleared to 0, by asserting
the INT[5:0]*, NMI* or RESET* signals. The Status register IntMask field has no effect on the return to Active
mode from Doze mode. The TMPR3901F will execute the corresponding exception handler for any unmasked
INT[5:0]* interrupt as well as the RESET* and NMI* interrupts. When an INT[5:0]* signal is used to return to
Active mode from Doze mode, and that signal's corresponding bit is masked in the IP field of Status register,
the TMPR3901F will resume execution of the instruction following the last instruction executed prior to
entering Doze mode.
The TMPR3901F sets the DOZE signal according to the status of the Doze bit in the Config register.
Output signals of the memory interface during Doze mode are the same as when a bus operation is not in
progress.