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Table 6-3. ExcCode field
ExcCode Field of Cause Register
No. Mnemonic Cause
0 Int External interrupt
1 Mod TLB Modified exception
2 TLBL TLB Refill exception (load instruction or instruction fetch)
3 TLBS TLB Refill exception (store instruction)
4 AdEL Address Error exception (load instruction or instruction fetch)
5 AdES Address Error exception (store instruction)
6 IBE Bus Error (instruction fetch) exception
7 DBE Bus Error (data load instruction or store instruction) exception
8 Sys System Call exception
9 Bp Breakpoint exception
10 RI Reserved Instruction exception
11 CpU Coprocessor Unusable exception
12 Ov Arithmetic Overflow exception
13-31 - reserved
6.2.2 EPC (Exception Program Counter) register (register no.14)
The EPC register is a 32-bit read-only register that stores the address at which processing should
resume after an exception ends.
The address placed in this register is the virtual address of the instruction causing the exception. If it
is an instruction to be executed during a branch (the instruction in the branch delay slot), the virtual
address of the immediately preceding branch instruction is placed in the EPC instead. In this case,
the BD bit in the Cause register is set to 1.
31 0
EPC
32
Figure 6-3. EPC register