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TMPR3901F
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Chapter 5 Power-Down Mode
The TMPR3901F has the following four power-down modes to enable lower power dissipation through
control of the internal clock.
• Halt mode
• Standby mode
• Doze mode
• Reduced Frequency mode
5.1 Halt mode
Figure 5-1 shows a state diagram of power down mode.
The TMPR3901F stops internal operations in Halt mode to reduce power dissipation. Setting the Config
register Halt bit to 1 switches from Active mode to Halt mode. During Halt mode, the TMPR3901F will
assert the HALT signal, stall the pipeline in holding currentstatus and cease to recognize bus requests.
If an instruction attempts to switch to Halt mode (by setting the Config register Halt bit to 1) during a bus
operation, the HALT signal will not be asserted until completion of the bus operation. If a switch to Halt
mode is attempted when a device other than the TMPR3901F owns the bus, the HALT signal will not be
asserted until the TMPR3901F regains bus mastership. Write operations will continue even in Halt mode, if
the write buffer contains data, until the buffer is emptied. SYSCLK and FCLK continue to run in Halt mode.
The TMPR3901F can be returned from Halt mode to Active mode, and the Halt bit cleared to 0, by asserting
the INT[5:0]*, NMI* or RESET* signals. The Status register IntMask field has no effect on the return to
Active mode from Halt mode. The TMPR3901F will execute the corresponding exception handler for any
unmasked INT[5:0]* interrupt as well as the RESET* and NMI* interrupts. When an INT[5:0]* signal is used
to return to Active mode from Halt mode, and that signal's corresponding bit is masked in the IP field of the
Status register, the TMPR3901F will resume execution of the instruction following the last instruction
executed prior to entering Halt mode.
Figure 5-1 State diagram of power-down mode
RF←not 00RF←00
Interrupt(RF≠00)
Halt←1
Doze←1
Interrupt (RF=00)
Doze
(Snoop enable)
Active
Halt
(Snoop disable)
Standby
Reduced frequency
(1/2, 1/4, 1/8)
Halt←1
Doze←1
Interrupt(RF=00)
Interrupt(RF≠00)