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TMPR3901F
203
Address
Protection
Unit
Debug
Support
Unit
R3900 Processor Core
1KB
Data
Cache
4KB
Instruction
Cache
CPU core
Bus Controller / Write Buffer
System
Interface
Interrupt
Reset
Real-time
Debugger
Interface
Synchroni-
zer
Clock
Generator
1.2 Internal Blocks
The TMPR3901F comprises the following blocks (Figure 1-1).
(1) R3900 Processor Core
(2) Clock generator
A quadruple-frequency PLL is built in and operates from an external crystal generator. For lower
power consumption, PLL oscillation can be halted externally.
(3) Bus interface unit (bus controller / write buffer)
This unit controls TMPR3901F bus operations. It includes a four-deep write buffer and has separate
32-bit data and address buses. Half-speed bus mode is supported in which bus operations run at half
the frequency of the internal clock. Bus arbitration is provided.
(4) Address protection unit
This unit will raise an exception when an attempt is made to access a predesignated address. It is
used to prevent access to certain memory areas. For example, the instructions or data in cache
memory can be protected using this nuit.
(5) Debug support unit
This unit supports a debug monitor and external real-time debugging system. A hardware break and
other functions are provided.
Figure 1-1 TMPR3901F block diagram