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Architecture
117
BEQL Branch On Equal Likely BEQL
31 26 25 21 20 16 15 0
BEQL
010100
rs rt offset
6 5 5 16
Format :
BEQL rs, rt, offset
Description :
Generates the branch target address by adding the address of the instruction in the delay slot to the
16-bit offset (that has been left-shifted two bits and sign-extended to 32 bits). It compares the
contents of general registers rs and rt and, if equal, the program branches to the target address after a
one-cycle delay. If the branch is not taken, the instruction in the delay slot is treated as a NOP.
Operation :
T:
T + 1:
target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR[rs] = GPR[rt])
if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
Exceptions :
None