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Architecture
174
SH Store Halfword SH
31 26 25 21 20 16 15 0
SH
101001
base rt offset
6 5 5 16
Format :
SH rt, offset(base)
Description :
Generates an unsigned 32-bit effective address by sign-extending the 16-bit offset and adding it to
the contents of general-purpose register base. It then stores the least significant halfword of register
rt at the resulting effective address. If the effective address is not aligned on a halfword boundary,
that is if the least significant bit of the effective address is not 0, an Address Error exception is
raised.
Operation :
T:
vAddr ← ((offset
15
)
16
||
offset
15..0
)
+ GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
31..2
||(pAddr
1..0
xor (ReverseEndian || 0))
byte ← vAddr
1..0
xor (BigEndianCPU || 0)
data ←GPR[rt]
31-8*byte..0
|| 0
8*byte
StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA)
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
TLB Modified exception (reserved)
Address Error exception