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TMPR3901F
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5.2 Standby Mode
Stopping the PLL clock in the TMPR3901F results in even less power dissipation than in Halt mode. This is
referred to as standby mode.
To transit from Active mode to Standby mode, first set the Halt bit the config register to 1. Then, follow the
sequence below to empty the write buffer. Finally, set the Halt bit to 1 using the MTC0 instruction.
SYNC
NOP
Loop : BC0F Loop
NOP
Figure 5-2 shows how stop the PLL and go to Standby mode.
Figure 5-3 shows how to return from Standby mode to Halt mode.
See the TMPR3901F Technical Data sheet for the timing.
Figure 5-3 Standby mode (PLL start)
Figure 5-2 Standby mode (PLL stop)
HALT
CLKEN
SYSCLK
PLLOFF*
Tclkoff
Tplloff
Tsys
HALT
CLKEN
SYSCLK
PLLOFF*
Tsta2
INT[5:0]*
NMI*
RESET*