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6.3.9 Reset exception
• Cause
− The reset signal in the R3900 Processor Core is asserted and then de-asserted.
• Exception mask
The Reset exception is not maskable.
• Processing
− A special interrupt vector (0xBFC0 0000) that resides in an uncached area is used. It is
therefore not necessary for hardware to initialize cache memory in order to process this
exception.
− The contents of all registers in the R3900 Processor Core become undefined. See the description
of each register earlier in this section for details.
− All data cache and instruction cache valid bits are cleared to 0, as are all data cache lock bits.
− If a Reset exception is raised during a bus cycle, the bus cycle is immediately ended and the reset
is allowed to proceed.