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Architecture
99
Load and Store Instructions
With the R3900 Processor Core, the instruction immediately following a load instruction can use the loaded
value. Hardware is interlocked for this purpose, causing a delay of one instruction cycle. Programming
should be carried out with an awareness of the potential effects of the load delay slot.
The descriptions of load/store operations make use of the functions listed in Table A-2 in describing the
handling of virtual addresses and physical memory.
Table A-2. Common Load/Store Functions
Function Meaning
AddressTranslation A memory management unit (MMU) is used to find the physical
address based on a given virtual address.
LoadMemory The cache and main memory are used to find the contents of the
word containing the designated physical address. The low-order
two bits of the address and the access type field indicate which of
the four bytes in the data word are to be returned. If the cache is
enabled for this access, the whole word is returned and loaded into
the cache.
StoreMemory The cache, write buffer and main memory are used to store the
word or partial word designated as data in the word containing the
designated physical address. The low-order two bits of the
address and the access type field indicate which of the four bytes
in the data word are to be stored.
The access type field indicates the size of data to be loaded or stored, as given in Table A-3. An address
always designates the byte with the smallest byte address in the addressed field, regardless of the access type
or the order in which bytes are numbered (endian). This is the left-most byte if big endian is used and the
right-most byte if little endian is used.