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Architecture
144
JR Jump Register JR
31 26 25 21 20 6 5 0
SPECIAL
000000
rs
0
000 0000 0000 0000
JR
001000
6 5 15 6
Format :
JR rs
Description :
Causes the program to jump unconditionally to the address in general register rs after a delay of one
instruction cycle.
Since instructions must be aligned on a word boundary, the two low-order bits of target register rs
must be 00. If not, an Address Error exception will be raised when the target instruction is fetched.
Operation :
T:
T + 1:
temp ← GPR[rs]
PC ← temp
Exceptions :
None