Toshiba TX39 Computer Hardware User Manual


 
Architecture
191
SWR Store Word Right (cont.) SWR
Operation :
T:
vAddr ((offset
15
)
16
||
offset
15..0
)
+ GPR[base]
(pAddr, uncached) AddressTranslation (vAddr, DATA)
pAddr pAddr
31..2
|| (pAddr
1..0
xor ReverseEndian
2
)
If BigEndianMem = 0 then
pAddr pAddr
31..2
|| 0
2
endif
byte vAddr
1..0
xor BigEndianCPU
2
data GPR[rt]
31-8*byte
|| 0
8*byte
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
TLB Modified exception (reserved)
Address Error exception