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Table 6-1. Exceptions defined for the R3900 Processor Core
Exception Mnemonic Cause
Reset Reset
†
This exception is raised when the reset signal is de-asserted after
having been asserted.
UTLB Refill UTLB Reserved for an MMU with TLB.
TLB Refill TLBL (load)
TLBS (store)
Reserved for an MMU with TLB. Used for exception request by a
memory access protection circuit. This exception is raised when
access is attempted to a protected memory area.
TLB Modified Mod Reserved for an MMU with TLB.
Bus Error IBE (instruction)
DBE (data)
An external interrupt raised by a bus interface circuit. A Bus Error
exception is raised when an event such as bus time-out, bus parity
error, invalid memory address or invalid access type is detected,
causing the bus-error pin to be asserted.
Address Error AdEL (load)
AdES (store)
This exception occurs with a misaligned access or an attempt to
access a privileged area in user mode. Specific causes are:
• Load, store or instruction fetch of a word not aligned on a word
boundary.
• Load or store of a halfword not aligned on a halfword boundary.
• Access attempt to kseg (including kseg0, kseg1, kseg2) in user
mode.
Overflow Ov This exception is raised for a two's complement overflow occurring
with an add or subtract instruction.
System Call Sys This exception is raised when a SYSCALL instruction is executed.
Breakpoint Bp This exception is raised when a BREAK instruction is executed.
Reserved
Instruction
RI This exception is raised when an undefined or reserved instruction
is issued.
Coprocessor
Unusable
CpU This exception is raised when a coprocessor instruction is issued
for a coprocessor whose CU bit in the corresponding Status
register is not set.
Interrupt Int This exception is raised when an interrupt condition occurs.
Non-maskable
Interrupt
NmI
†
This exception is raised at the falling edge of the non-maskable
interrupt signal.
Debug Exception Debug Single Step exception and Debug Breakpoint exception.
See chapter 8 for detail
†
Not an ExcCode mnemonic.