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TMPR3901F
212
(2) INT[5:0]*
The INT[5:0]* signal is synchronized with the processor clock in phase with SYSCLK (Figure 2-4).
Figure 2-4 INT* signal synchronization
Interrupt detection
SYSCLK
INT*(external)
INT*(internal)
(a) Full-speed bus mode
Instruction at
interrupt
handler starts
F D E M
F D E
Interrupt detection
(b) Half-speed bus mode
F D E M
F D E
SYSCLK
Processor clock
INT*(external)
Instruction at
interrupt
handler starts
INT*(internal)