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Architecture
196
Bit Encoding of CPU Instruction Opcodes
Figure A-2 shows the bit codes for all CPU instructions (ISA and extended ISA).
OPcode
28..26
31..29 0 1 2 3 4 5 6 7
0 SPECIAL BCOND J JAL BEQ BNE BLEZ BGTZ
1 ADDI ADDIU SLTI SLTIU ANDI ORI XORI LUI
2 COP0 COP1 COP2 COP3
BEQLδ BNELδ BLEZLδ BGTZLδ
3 * * * * MADD/
MADDUδ
* * *
4 LB LH LWL LW LBU LHU LWR *
5 SB SH SWL SW * * SWR
CACHEδ
6 *
ξ ξ ξ
* * * *
7 *
ξ ξ ξ
* * * *
SPECIAL function
2.0
5..3 0 1 2 3 4 5 6 7
0 SLL * SRL SRA SLLV * SRLV SRAV
1 JR JALR * * SYSCALL BREAK
SDBBPδ SYNCδ
2 MFHI MTHI MFLO MTLO * * * *
3 MULT MULTU DIV DIVU * * * *
4 ADD ADDU SUB SUBU AND OR XOR NOR
5 * * SLT SLTU * * * *
6 * * * * * * * *
7 * * * * * * * *
BCOND
18..16
20..19 0 1 2 3 4 5 6 7
0 BLTZ BGEZ
BLTZLχ BGEZLχ γ γ γ γ
1
γ γ γ γ γ γ γ γ
2 BLTZAL BGEZAL
BLTZALLχ BGEZALLχ γ γ γ γ
3
γ γ γ γ γ γ γ γ
COPz rs
23..21
25,24 0 1 2 3 4 5 6 7
0 MF
γ
CF
γ
MT
γ
CT
γ
1 BC
γ γ γ γ γ γ γ
2
3
CO
Figure A-2. Operation Code Bit Encoding