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Architecture
187
SW Store Word SW
31 26 25 21 20 16 15 0
SW
101011
base rt offset
6 5 5 16
Format :
SW rt, offset(base)
Description :
Generates a 32-bit effective address by sign-extending the 16-bit offset value and adding it to the
contents of general-purpose register base. It then stores the contents of register rt at the resulting
effective address.
If the effective address is not aligned on a word boundary, that is, if the low-order two bits of the
effective address are not 00, an Address Error exception is raised.
Operation :
T:
vAddr ← ((offset
15
)
16
||
offset
15..0
)
+ GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
data ←GPR[rt]
StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA)
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
TLB Modified exception (reserved)
Address Error exception