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7.5 Cache Snoop
The R3900 Processor Core has a bus arbitration function that releases bus mastership to an external bus
master. Consistency between cache memory and main memory could deteriorate when an external bus master
has write access to main memory. The purpose of the cache snoop function is to maintain this data
consistency.
When the R3900 Processor Core releases the bus, the bus cycle is snooped by an external bus master. If an
address access by the external bus master matches an address stored in the on-chip data cache (cache hit), the
valid bit (V) for that cache data is cleared to 0, invalidating it.
Locked data cannot be invalidated, however, even when a hit occurs in a snoop operation.
After a cache block has been invalidated in a snoop, the LRU bit points to the invalidated cache set.
The lock bit is not changed as the result of a snoop.
Note : A snoop is possible even when the data cache is disabled.
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