Filter
Top Products
Architecture
12
The instruction set is classified as follows.
(1) Load/store
These instructions transfer data between memory and general registers. All instructions in this group
are I-type. “Base register + 16 bit signed immediate offset” is the only supported addressing mode.
(2) Computational
These instructions perform arithmetic, logical and shift operations on register values. The format can
be R-type (when both operands and the result are register values) or I-type (when one operand is 16-
bit immediate data).
(3) Jump/branch
These instructions change the program flow. A jump is always made to a 32 bit address contained in
a register (R-type format ), or to a paged absolute address constructed by combining a 26-bit target
address with the upper 4 bits of the program counter (J-type format). In a branch instruction, the
target address is made up of the program counter value plus a 16 bit offset.
(4) Coprocessor
These instructions execute coprocessor operations. Each coprocessor has its own format for
computational instructions.
Note : Coprocessor load instruction LWCz and coprocessor store instruction SWCz are not
supported by the R3900 Processor Core. An attempt to execute either of these instructions
will trigger a Reserved Instruction exception.
(5) Coprocessor 0
These instructions are used for operations with system control coprocessor (CP0) registers, processor
memory management and exception handling.
Note : TLB (Translation Lookaside Buffer) instructions (TLBR, TLBWJ, TLBWR and TLBP) are
not supported by the R3900 Processor Core. These instructions will be treated by the R3900
as NOP(no operation).
(6) Special
These instructions support system calls and breakpoint functions. The format is always R-type.