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TMPR3901F
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The BUSREQ* signal is confirmed on the rising edge of SYSCLK. If no bus operation is currently
in progress, the BUSGNT* signal is asserted in the next clock after the BUSREQ* assertion is
confirmed. The TMPR3901F stops driving the bus in the next clock, thus releasing it.
During the time the bus is released by the TMPR3901F, the pin states related to bus operation are as
follows.
BUSGNT*
L
D [31:0] high impedance
BE [3:0]*
high impedance
RD*, WR*
high impedance
LAST*
high impedance
BSTART*
high impedance
BURST*
high impedance
BSTSZ [1:0] high impedance
A [31:2] input
HALT, DOZE no change
4.5.2 Cache snoop
During the time the bus is released by the TMPR3901F, the on-chip data cache can be snooped. An
external circuit asserts the SNOOP* signal and drives an address on A[31:2]. The TMPR3901F
latches the address in the same clock in which it confirms the SNOOP* signal assertion. The snoop
then takes place at that address in the on-chip data cache.
If the snoop address results in a data cache hit, that cache entry is invalidated.
SNOOP* is valid only while a BUSGNT* signal is asserted.