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Architecture
34
(d) BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BGEZALL (ISA Extended Set)
Instruction Format and Description
Branch on
Equal Likely
BEQL rs, rt, offset
Branch to the target if the contents of registers rs and rt are equal.
Branch on Not
Equal Likely
BNEL rs, rt, offset
Branch to the target if the contents of registers rs and rt are not equal.
Branch on
Less Than or
Equal Zero
Likely
BLEZL rs, offset
Branch to the target if register rs is 0 or less.
Branch on
Greater Than
Zero Likely
BGTZL rs, offset
Branch to the target if register rs is greater than 0.
Instruction Format and Description
Branch on
Less Than
Zero Likely
BLTZL rs, offset
Branch to the target if register rs is less than zero
Branch on
Greater Than
or Equal Zero
Likely
BGEZL rs, offset
Branch to the target if register rs is 0 or greater.
Branch on
Less Than
Zero And Link
Likely
BLTZALL rs, offset
Store in r31 (link register) the address of the instruction following the instruction
in the delay slot (the one to be executed during the branch). If register rs is less
than 0, branch to the target.
Branch on
Greater Than
or Equal Zero
And Link
Likely
BGEZALL rs, offset
Store in r31 (link register) the address of the instruction following the instruction
in the delay slot (the instruction in the delay slot is executed during the branch).
If register rs is 0 or greater, branch to the target.
rs
rs
offset
offset
rt
funct
op
op