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TMPR3901F
223
BUSERR* is valid until the clock cycle in which the last data is read. In the clock cycle in which the
TMPR3901F recognizes the assertion of BUSERR*, the TMPR3901F ends the burst read cycle and
raises a Bus Error exception (see Figure 4-4).
When a bus error occurs in a burst read, only those cache lines for which complete reads were
accomplished are refilled.
Figure 4-4 Bus error in burst read operation (4 words)
SYSCLK
A[31:2]
BE[3:0]*
RD*
BSTART*
LAST*
BURST*
BSTSZ[1:0]
ACK*
BUSERR*
D[31:0]
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