Filter
Top Products
Architecture
88
(2) Debug exception handling
i) Raising a debug exception
n DEPC and Debug register updates
DEPC : The address where the exception was raised is put in this register.
DBD : Set to 1 when the exception was raised for an instruction in the branch delay slot.
DM : Set to 1.
DSS, DBp : Set to 1 if the corresponding exception was raised.
NIS : Set to 1 if a Non-maskable interrupt occurred at the same time as the debug
exception.
OES : Set to 1 if another exception (other than reset, NmI, or UTLB Refill) was raised at
the same time as the debug exception.
n Branching to a debug exception handler
PC : 0xBFC0 0200
(Note : Registers other than DEPC and Debug retain their values.)
n Masking of exceptions and interrupts in a debug exception handler
A load or store instruction for which a TLB-related exception (TLB Refill, UTLB Refill, TLB
Modified) is raised becomes a NOP; the bus cycle is not executed, and the TLF bit is set.
When a bus error exception is requested for a load or store instruction, BsF is set. The
load/store result in this case is undefined.
A Non-maskable interrupt request is held internally, and is raised upon return from the debug
exception handler.
Single Step debug exception is disabled.
Debug interrupts are ignored and not raised.
(Note : The result of exceptions or interrupts other than those noted above is undefined.
Resets are allowed to occur.)
n Cache lock function
This function is disabled regardless of the Cache register value.
ii) Debug exception handler execution
When a debug exception occurs, the user program should determine the nature of the exception from
the Debug register bits (DSS, DBp) and invoke the corresponding exception handler.