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Architecture
134
CACHE Cache (cont.) CACHE
Bits 20..18 of the Cache instruction select the operation to be performed as follows.
Bit#
Cache Operation Description
20 19 18
ID Name
0 0 0 I IndexInvalidate Sets the cache state of the cache block to
Invalid. This instruction is valid only
when the instruction cache is invalid
(Config register ICE bit is 0).
0 0 1 D IndexLRUBitClear Clears the LRU bit of the cache at the
designated index.
0 1 0 D IndexLockBitClear Clears the Lock bit of the cache at the
designated index.
1 0 0 D HitInvalidate If a cache block contains the designated
address, sets that cache block to Invalid.
Operation :
T:
vAddr ← ((offset
15
)
16
|| offset
15..0
) + GPR[base]
(pAddr, uncached ← AddressTranslation (vAddr, DATA)
Exceptions :
Coprocessor Unusable exception