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TMPR3901F
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(d) Break Status register (BSts)
The break status register is used to set conditions for exception requests.
MInv [9] (Master Overlay Invert)
If this bit is set to 1, exception requests are triggered by an XOR of the channel 0 and channel
1 address comparison results.This means that an exception request occurs if the address
comparison is true (the address matches) for only one of the two channels. The exception
request does not occur if both channels have matching addresses.
If this bit is cleared to 0, exception requests are triggered by an OR of the channel 0 and
channel 1 address comparison results. This means that an exception request occurs if either
channel has a matching address.
Using this bit, a nonbreak address can be set in a break address area.
MEn [8] (Master Enable)
If this bit is set to 1, exception requests are enabled.
If this bit is cleared to 0, exception requests are disabled.
0 on reset.
St [1:0] (Status)
The St bit shows whether or not a channel had a matching address on the last memory
protection exception. St[1] is for channel 1, and St[0] is for channel 0.
If the channel address matches, the bit is set to 1; if it does not match the bit is cleared to 0.
When both channels addresses match, both bits are set to 1.
The St bits are not set when the MEn bit is 0.
The St bits are not set when the MInv bit is 1 and both channels have matching addresses.
The St bit can be cleared to 0 by writing 0 to it.
2.4.2 Memory protection exception
The R3000A compatible MMU TLB Refill exceptions are used.
A TLBL exception is signaled whenever an instruction fetch or data read violation occurs. The TLBS
exception is signaled when a data store violation occurs.
When memory protection exception occurs at the same time as a non-maskable interrupt exception
(NmI) or bus error exception (IBE, DBE), the non-maskable interrupt exception or bus error exception
is handled according to priority. However, the BSts register St bit is set to 1.
31
0
9
8
10
5
6
7
3
4
0
1
2
0
MEn
MInv
0
0
0
St
0
0