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Architecture
62
6.2.8 Config (Configuration) register (register no.3)
This register designates the R3900 Coprocessor Core configuration.
31 21 19 18 16 11 10 9 8 7 6 5 4 3 2 1 0
0 ICS DCS 0 RF IRSize DRSize
Bits Mnemonic Field name Description
Value on
Reset
Read/
Write
21-19 ICS Instruction
Cache Size
Indicates the instruction cache size.
000: 1 KB;
001: 2 KB;
010: 4 KB;
011: 8 KB;
1xx : (reserved)
†
Read
18-16 DCS Data Cache
Size
Indicates the data cache size.
000: 1 KB;
001: 2 KB;
010: 4 KB;
011: 8 KB;
1xx : (reserved)
†
Read
11-10 RF Reduced
Frequency
Controls clock divider to determine
reduced frequency provided
externally from R3900 master clock.
Please refer product's user manual
for detail.
00 Read/
Write
9 Doze Doze
††
Setting this bit to 1 puts the R3900
Processor Core in Doze mode and
stalls the pipeline. This state is
canceled by a Reset exception when
a reset signal is received, or when
cancelled by a non-maskable
interrupt signal or interrupt signal
that clears the Doze bit to 0. The
Doze bit is cleared even if interrupts
are masked. Data cache snoops
are possible during Doze mode.
0 Read/
Write
†
implemented cache size
†† Operation is undefined when both Doze bit and Half bit are set to 1.
Figure 6-10. Config register (1/2)
Doze
Halt
Lock
DCBR
ICE
DCE