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6.2.4 Cache register (register no.7)
This register controls the cache lock function.
31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 IAL
o
DAL
o
IAL
p
DAL
p
IAL
c
DAL
c
0
18 1 1 1 1 1 1 0
Bits Mnemonic Field name Description
Value on
Reset
Read/
Write
13 IALo Instruction Cache
Lock(old)
1 = cache lock enable;
0 = cache lock disable
0 Read/
Write
12 DALo Data Cache
Lock(old)
1 = cache lock enable;
0 = cache lock disable
0 Read/
Write
11 IALp Instruction Cache
Lock(previous)
1 = cache lock enable;
0 = cache lock disable
0 Read/
Write
10 DALp Data Cache
Lock(previous)
1 = cache lock enable;
0 = cache lock disable
0 Read/
Write
9 IALc Instruction Cache
Lock(current)
1 = cache lock enable;
0 = cache lock disable
0 Read/
Write
8 DALc Data Cache
Lock(current)
1 = cache lock enable;
0 = cache lock disable
0 Read/
Write
31-14
7-0
0 Ignored on write; 0 when read. 0 Read
Figure 6-5. Cache register